Description
NVIDIA is hiring a Senior Mask Layout Design Engineer to perform physical layout of mixed-signal functions such as PLLs, high-speed SerDes, analog-to-digital converters, and ESD structures in sub-micron CMOS technologies using Cadence tools. The role involves floor planning, custom layout, design-rule and schematic verification, and cross-functional work with ASIC and mixed-signal engineers. Candidates need a BSEE or equivalent, at least seven years of mask and layout design experience, expertise in analog CMOS layout, Cadence Virtuoso, verification tools, scripting, and DRC/LVS flows. The posting is marked hybrid and lists base salary ranges for Level 4 and Level 5 engineers.
