Description
NVIDIA is hiring a Senior Mask Layout Design Engineer to perform physical layout of mixed-signal functions, high-speed datapaths, and high-speed clocking designs in sub-micron CMOS technologies using Cadence tools. The role involves floor planning, custom layout, design-rule and schematic verification, and collaboration with mixed-signal design engineers on chiplet interface projects. Candidates need a BSEE or equivalent, at least five years of mask and layout design experience, FinFET technology expertise, Virtuoso proficiency, and knowledge of DRC and LVS flows.
