Description
NVIDIA is hiring a Senior Mask Layout Design Engineer to perform physical layout of mixed-signal functions, high-speed datapaths, and high-speed clocking designs in sub-micron CMOS technologies using Cadence tools. The role involves floor planning, custom layout, design-rule and schematic verification, and collaboration with mixed-signal design engineers on chiplet interface projects. Candidates need a BSEE or equivalent, at least 8 years of mask and layout design experience, FinFET expertise, Virtuoso proficiency, DRC and LVS knowledge, and strong teamwork and communication skills. The posting offers a hybrid work arrangement and a base salary of 132,000–207,000 USD for Level 4 and 148,000–235,750 USD for Level 5, with equity and benefits.
