Description
NVIDIA is hiring a Senior Mask Layout Design Engineer to perform physical layout of mixed-signal functions such as PLLs, high-speed I/O, general I/O, and ESD structures in sub-micron CMOS technologies using Cadence tools. The role collaborates with ASIC and mixed-signal engineers, customizes designs for VLSI integration, and performs floor planning, custom layout, and DRC/LVS verification. Candidates need a BSEE or equivalent, at least five years of relevant mask design or layout experience, expertise in analog CMOS layout and Cadence Virtuoso, and experience with DRC/LVS verification tools and scripting languages.
