Description
NVIDIA is hiring Senior Physical Design Engineers for its Networking Silicon engineering team to lead physical design and implementation of SOC devices for networking markets. The role covers partition and chiplet-level work, including RTL-to-GDS development, chip floorplanning, power and clock distribution, place-and-route, timing closure, power and noise analysis, physical verification, and design-flow development. Candidates need a BSEE or MSEE or equivalent, five years of VLSI physical design experience on 5nm, 4nm, and 3nm technologies, a successful production-tapeout record, and strong EDA tool and debugging expertise. The base salary range is 136,000–218,500 USD for Level 3 and 168,000–264,500 USD for Level 4, with equity and benefits; applications were accepted through October 6, 2026.
