Description
Google is hiring an ASIC Physical Design Engineer to develop RTL-to-GDS implementation for high Power, Performance, and Area designs, manage full-chip physical implementation, and improve performance and power. The role requires a bachelor's degree in Electrical Engineering or equivalent practical experience, eight years of physical design experience, and experience with synthesis and PnR tools, STA, and sign-off optimization. Preferred qualifications include floorplanning, low-power implementation, ASIC design methodology, computer architecture, Verilog/SystemVerilog, circuit design, device physics, and scripting skills. The position offers $163,000–$236,000 USD plus a 15% bonus target, equity, and benefits, and typically requires in-person interviews.
