Description

Astera Labs is seeking a Senior Principal ASIC Design Engineer to lead the design of next-generation Ethernet and Scale-Up (ESUN) connectivity products. This role involves defining and driving ASIC architecture, leading RTL design and microarchitecture development, and ensuring robust, manufacturable silicon. The engineer will also architect hardware acceleration for NIC functions, RDMA, DMA, virtualization, and protocol offloads, and partner with firmware and software teams.

Required Skills

RTL design
microarchitecture
high-performance networking
networking ASICs
Ethernet controllers
MACs
NIC architectures
packet processing engines
network interface subsystems
RDMA architectures
RoCE
InfiniBand
low-latency networking technologies
packet parsing
scheduling
DMA
queue management
flow control
congestion management
transport acceleration
high-speed interconnects
Ethernet
PCIe
AI scale-up fabrics
ASIC development flow
architecture
synthesis
timing closure
physical implementation
tapeout
post-silicon validation
technical leadership

Additional Information

Required Previous Experiences: 12+ years of ASIC/SoC design experience, with a track record of delivering complex, high-speed networking or connectivity silicon from architecture through production.
Deep expertise in RTL design and microarchitecture for high-performance networking and connectivity ASICs.
Extensive experience designing Ethernet controllers, MACs, NIC architectures, packet processing engines, or network interface subsystems.
Strong understanding of RDMA architectures and transport protocols such as RoCE, InfiniBand concepts, or similar low-latency networking technologies.
Experience designing hardware for packet parsing, scheduling, buffering, DMA, queue management, flow control, congestion management, and transport acceleration.
Hands-on experience across the complete ASIC development flow, including architecture, RTL design, integration, synthesis, timing closure, physical implementation, tapeout, and post-silicon validation.
Demonstrated technical leadership across multiple teams and product programs.
Preferred Qualifications: Master’s or PhD in Electrical Engineering, Computer Engineering, or a related technical discipline.
Direct experience with UALink, UCIe, PCIe Gen 6/7, and/or advanced Ethernet architectures and protocols.
Experience designing Ethernet MACs, controllers, SmartNICs, DPUs, NICs, switch datapaths, or packet processing engines.
Experience developing Ethernet-based scale-up networking solutions for AI and HPC systems.
Experience leading architecture or design for multiple successful advanced-node ASIC tapeouts.
Excellent communication, collaboration, and mentorship skills.
Translation Company Name: Astera Labs

About Astera Labs

Astera Labs

Silicon-based hardware connectivity solutions and software for rack-scale AI.San Jose, CA, United States

Astera Labs builds silicon-based hardware connectivity solutions and software for rack-scale AI, including smart fabric switches, retimers, memory controllers, and signal conditioners. Astera Labs reported second-quarter 2026 revenue of $392.4 million, up 27% quarter over quarter and 104% year over year.

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Senior Principal ASIC Design Engineer at Astera Labs

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About Astera Labs

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