Compensation
$205,000 – $255,000/yr
Astera Labs is looking for a Senior Principal Digital Design Engineer to lead the architecture and implementation of next-gen digital designs for AI infrastructure connectivity. This role involves defining micro-architecture strategies, making complex chip-level design decisions, and guiding multiple blocks from concept to silicon bring-up. The engineer will also shape design methodologies, mentor teams, and collaborate cross-functionally to deliver high-performance silicon.
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Silicon-based hardware connectivity solutions and software for rack-scale AI.San Jose, CA, United States
Astera Labs builds silicon-based hardware connectivity solutions and software for rack-scale AI, including smart fabric switches, retimers, memory controllers, and signal conditioners. Astera Labs reported second-quarter 2026 revenue of $392.4 million, up 27% quarter over quarter and 104% year over year.