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Senior RTL Engineer, Packet-Networking and Interconnect at OpenAI

Department: Scaling

Compensation

$225,000 – $445,000/yr

Setup
Hybrid
Location
San Francisco, California
Level
senior
Posted

Description

OpenAI is hiring a senior RTL Engineer to own the microarchitecture, SystemVerilog implementation, verification, physical design convergence, silicon bring-up, and production readiness of on-chip and off-chip packet-networking and interconnect components for a custom AI accelerator platform. The role includes designing NoC fabrics, switches, routers, protocol adapters, traffic-management logic, and custom networking protocols, while leading junior engineers and collaborating with architecture, verification, physical design, firmware, performance, and post-silicon teams.

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