Description
OpenAI is hiring a senior RTL Engineer to own the microarchitecture, SystemVerilog implementation, verification, physical design convergence, silicon bring-up, and production readiness of on-chip and off-chip packet-networking and interconnect components for a custom AI accelerator platform. The role includes designing NoC fabrics, switches, routers, protocol adapters, traffic-management logic, and custom networking protocols, while leading junior engineers and collaborating with architecture, verification, physical design, firmware, performance, and post-silicon teams.
