Description
The Formal Verification Engineer will apply formal verification methodologies to complex IP, subsystems, and SoCs, developing proof strategies, assertions, properties, verification environments, automation, and coverage closure. The role requires a relevant bachelor's or master's degree, at least four years of formal verification experience, and hands-on knowledge of Verilog, SystemVerilog, SVA, temporal logic, protocol verification, and RTL analysis. The position collaborates with architecture, design, firmware, emulation, FPGA, validation, and post-silicon teams and may involve hybrid working.
