Senior SoC Power Analysis & Optimization Engineer at MatX

Department: Hardware

Compensation

$160,000 – $275,000/yr

Setup: Hybrid
Location: Huntington Beach, California
Type: Full-time
Level: senior
Posted: Jul 22, 2026

Description

MatX is hiring a Silicon Power Engineer to develop and maintain power estimation methodologies, build energy models, perform RTL, gate-level, and post-layout power analysis, and drive power optimization across AI accelerator SoC subsystems. The role collaborates with architects, RTL designers, and physical design teams, develops analysis automation, and presents optimization recommendations. Candidates need a BS or MS in a relevant engineering field, at least 8 years of SoC or high-performance digital design experience, ASIC low-power design experience, and scripting experience. The position offers a US base salary of $160,000–$275,000 for early-career candidates, plus equity and benefits.

Required Skills

Power estimation
Power analysis
ASIC low-power design
RTL power analysis
Python
Verilog/SystemVerilog
Clock gating
Power management

Additional Information

Minimum Education: Bachelor's or master's degree in Electrical Engineering, Computer Engineering, or a related field
Required Previous Experiences: 8+ years of industry experience in SoC, AI accelerator, GPU, networking ASIC, or high-performance digital design
Experience with ASIC low-power design techniques
Experience performing RTL and gate-level power analysis
Experience with Python, Perl, or similar scripting languages
Preferred Qualifications: RTL development experience using Verilog/SystemVerilog
Experience with clock distribution, multiple clock domains, clock gating, and power-aware RTL design
Experience with synthesis, static timing analysis, place-and-route, and implementation flows
Experience with power analysis tools such as Joules, PowerArtist, or PrimeTime PX
Experience developing power models, budgeting methodologies, and projection flows
Experience analyzing large power datasets using scripting and data analytics
Experience with power management techniques including clock gating, power gating, and dynamic power management
Experience correlating pre-silicon power estimates with silicon measurements
Experience with AI workload characterization and power-performance analysis