Description
Astera Labs is hiring a full-time Senior STA Engineer in Ahmedabad to own static timing analysis, timing signoff, and timing closure for complex ASIC/SoC designs. The role covers MCMM/MMMC analysis, SDC constraints, clock-tree and clock-domain timing, OCV/AOCV/POCV, SI/crosstalk, derating, and variation-aware timing, while collaborating with RTL, synthesis, physical design, ECO, and signoff teams. The engineer will also develop Tcl/Python automation, debug complex timing issues, mentor junior engineers, and support tape-out schedules.
