Senior Staff Analog Layout Engineer at Synopsys

Location: Bengaluru, Karnataka
Level: senior
Posted: Sep 24, 2026

Description

Synopsys is hiring a senior analog layout engineer to design full-custom analog layouts for UCIe PHY blocks and advanced 2.5D/3D chiplet integration. The role covers PHY floor planning, micro bump architecture, high-speed differential routing, signal integrity, physical verification, ASIC physical design integration, automation, technical reviews, and tape-out execution. Candidates need a relevant engineering degree, 8 to 15 years of analog or mixed-signal custom IC layout experience, and a proven record of UCIe PHY, SerDes, or die-to-die interface tape outs.

Required Skills

Analog layout
Floor planning
Micro bump planning
Differential routing
Signal integrity
Physical verification
LEF generation
Layout automation

Additional Information

Minimum Education: Diploma or Bachelor's degree in Electrical Engineering, Electronics Engineering, or a related technical field
Required Previous Experiences: 8 to 15 years of hands-on experience in analog or mixed-signal custom IC layout design
Experience designing UCIe PHY, high-speed SerDes, or die-to-die interface layouts with successful tape outs
Expertise in micro bump planning, bump map architecture, package-aware floor planning, and 2.5D/3D die/package co-design
Experience with high-speed differential routing and signal integrity optimization
Experience closing DRC, LVS, ERC, EM/IR, antenna, density, and reliability checks through tape out
Experience integrating analog layouts with ASIC physical design flows, LEF generation, and top-level verification
Preferred Qualifications: Experience integrating analog layouts with ASIC physical design flows, LEF generation, and top-level verification