Senior Staff Interface IP Verification Engineer (Pre-Silicon- PCIe/CXL/DDR/Ethernet) at Synopsys

Synopsys is hiring a Senior Staff Interface IP Verification Engineer to own end-to-end pre-silicon verification of Interface IP blocks including PCIe, CXL, DDR, and Ethernet. The role involves building scalable UVM-based verification environments, defining coverage-driven test plans, developing constrained-random test scenarios, debugging RTL and protocol issues, collaborating with architecture and design teams, and mentoring verification engineers. Candidates need a bachelor's or master's degree in electrical or computer engineering, at least 8 years of ASIC or SoC verification experience, and strong expertise in SystemVerilog, UVM, and at least one listed protocol.