Senior/Staff Mid-End Engineer (3D/Process Integration) at Bitdeer Technologies Group

Department: IC Lab

Location: Malaysia
Type: Full-time
Level: senior
Posted: Jun 25, 2026

Description

Bitdeer is hiring a 3D Chip Integration Engineer to own the definition and signoff of 3D stacked-die chip stacks, including TSV and hybrid-bond interfaces, 3D-aware floorplanning, DFM and design-rule reviews, thermal and thermal-mechanical analysis, SI/PI signoff, DFT test strategy, and package/substrate co-design handoff to OSAT. The role requires a degree in a relevant engineering field, at least five years of 3D integration or advanced-packaging experience, hands-on TSV and hybrid-bonding experience, and familiarity with a 3D foundry ecosystem such as TSMC 3DFabric.

Required Skills

TSV
Hybrid bonding
3D floorplanning
Thermal analysis
SI/PI
DFT
TSMC 3DFabric

Additional Information

Minimum Education: Bachelor's, master's, or PhD in electrical engineering, materials, mechanical engineering, or a related field
Required Previous Experiences: At least five years of 3D integration, advanced packaging, or process integration experience, including one product taken to tapeout and through assembly
Hands-on experience with TSV and hybrid bonding and a 3D stacking flow
Working knowledge of TSMC 3DFabric or an equivalent foundry 3D ecosystem
Preferred Qualifications: Experience with DRAM-on-logic stacks, HBM-class memory integration, or high-bandwidth memory interfaces
Background in AI or HPC accelerators or other high-power, high-bandwidth SoCs
Familiarity with thermal/mechanical tools such as Ansys and 3D physical/signoff flows using Synopsys or Cadence
Exposure to stacked-die test and yield debug
Experience establishing a 3D-integration methodology on a small team
Translation Company Name: Bitdeer Technologies Group