Description
Synopsys is hiring an LPDDR PHY RTL Design Engineer to design RTL modules for LPDDR PHY IP from microarchitecture through synthesis-ready implementation, optimize designs for timing, power, and area across advanced process nodes, develop Perl automation, and collaborate with architecture, analog, verification, and physical design teams. The role requires a bachelor's or master's degree in electrical or computer engineering, 10+ years of ASIC digital design experience with RTL ownership in production silicon, expert Verilog proficiency, strong Perl scripting skills, and deep knowledge of synthesis, timing analysis, and power optimization; PHY IP or high-speed interface experience is preferred.
