Senior Static Timing Analysis Methodology Lead Engineer / Technical Lead at Altera

Compensation

$187,000 – $270,000/yr

Location: San Jose, California
Type: Full-time
Level: senior
Posted: Aug 27, 2026

Description

Altera is hiring a senior FPGA timing design-automation engineer to own and lead static timing analysis flows and timing modeling methodology across ASIC, custom, and semi-custom IP designs. The role develops and releases production-grade flows, automation, regression infrastructure, and user support; partners with design, physical design, technology, reliability, and EDA vendor teams; and sets technical direction while mentoring engineers. The position is based in San Jose, California, with a stated salary range of $187,000 to $270,000 USD for the Bay Area.

Required Skills

Static Timing Analysis
Timing Modeling
Python
Tcl
Cell Characterization
SPICE Simulation
Regression Infrastructure
Technical Leadership

Additional Information

Minimum Education: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field
Required Previous Experiences: 10+ years of professional experience in semiconductor design automation, CAD/EDA engineering, ASIC/custom IC design, or a closely related field, including hands-on production design automation or timing flow development
10+ years of experience with Static Timing Analysis and timing sign-off methodology
10+ years of experience with timing analysis, cell characterization, and/or SPICE circuit simulation tools
10+ years of experience developing automation and software for engineering workflows
Experience owning and releasing production-grade design automation and CAD flows
Technical leadership in design automation or timing, including methodology direction and mentoring
Experience partnering with semiconductor design teams to define methodology, deploy flows, resolve issues, and support tape-outs
Experience leading cross-functional technical initiatives and influencing decisions across distributed teams
Preferred Qualifications: Experience owning block-level or full-chip STA methodology and timing closure flows through multiple production tape-outs
Advanced experience with cell characterization and Liberty model generation
Experience with transistor-level timing analysis, custom IP timing, SPICE simulation, or characterization flows
Experience developing or supporting FPGA timing models, timing collateral, or customer-facing timing deliverables
Experience with timing reliability, aging, derating, electromigration, or other reliability-aware methodologies
Experience with advanced-node timing challenges involving variation, signal integrity, crosstalk, multi-voltage designs, low-power methodologies, or complex MCMM sign-off
Experience evaluating and influencing roadmaps for major commercial EDA tools and vendors
Experience applying AI/ML techniques to design automation
Experience leading technical roadmaps, methodology modernization, or greenfield CAD/EDA infrastructure initiatives
Master's or Ph.D. degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field