Description
E-Space is hiring a Senior STA Methodology Engineer for its ASIC design team to own cross-functional static timing analysis methodology across multiple IPs, projects, and technology nodes. The role covers RTL-to-GDS timing flows, signoff correlation and closure, timing constraint debugging, ECO strategies, CAD utilities, and data-driven or ML-assisted STA improvements, while mentoring design and physical design engineers. Candidates need a BS or MS in Electrical or Computer Engineering or equivalent experience, at least 8 years of STA and timing-methodology experience, and strong PrimeTime and scripting expertise. The position is full-time and based in Santa Clara, with a target base pay of $120,000 to $220,000 annually.
