Description
The role is responsible for full-chip or subsystem static timing analysis and timing closure across multiple modes and corners. It involves using PrimeTime and/or Tempus, validating SDC constraints and clock coverage, debugging interface and block-to-block timing, analyzing OCV/AOCV/POCV and parasitic effects, generating timing ECO recommendations, and collaborating with RTL, synthesis, PnR, DFT, and methodology teams through signoff. The position requires 5–10 years of relevant STA or timing-closure experience, strong PrimeTime or Tempus expertise, and a BE/BTech/MTech in electronics, electrical engineering, or a related discipline.
