Description
Draper is hiring a Senior UVM Digital Verification Engineer in Cambridge, Massachusetts to develop and execute verification strategies for complex digital and mixed-signal FPGA and ASIC designs. The role involves writing verification and test plans, creating UVM agents and VIPs, performing coverage closure, using formal analysis tools, collaborating with RTL designers, and mentoring junior engineers. Candidates need 5-7 years of experience in systems analysis or related work, a bachelor’s degree in engineering (master’s preferred), strong SystemVerilog/UVM and scripting skills, and the ability to obtain and maintain a government security clearance.
