Description
proteanTecs is hiring a Senior VLSI Verification Engineer to develop and maintain scalable SystemVerilog and UVM verification environments, create comprehensive testbenches and random test suites, drive coverage closure, and lead debug and root-cause analysis for complex IP and SoC integration. The role requires a B.Sc. in Electrical or Computer Engineering, at least five years of VLSI verification experience, strong software development skills, and collaboration with architecture, design, and firmware teams. Experience with Git, Python, FPGA emulation, formal verification, and mixed-signal simulation is advantageous.
