Description
Synopsys is hiring a SerDes/DSP System, Sr Architect to develop and validate high-speed SerDes system models for PAM4 transceivers supporting PCIe, Ethernet, and other wireline and optical protocols. The role involves MATLAB/Simulink modeling, algorithm design, simulation sign-off, silicon measurement correlation, customer troubleshooting, and collaboration with analog, digital, and hardware engineering teams. Candidates need an M.Sc. or Ph.D. in Electrical or Computer Engineering and at least 13 years of relevant experience, along with expertise in DSP, communications theory, link budgets, high-speed circuit topologies, and C/Verilog-A/system Verilog.
