Description
The SerDes Implementation Lead will own the physical-layer implementation, register-level configuration, equalization tuning, post-silicon bring-up, characterization, and debugging of 112G and 224G PAM4 ultra-high-speed data links. The role requires hands-on experience with high-speed SerDes, signal and power integrity, high-bandwidth test equipment, Python-based lab automation, and collaboration with SI/PI, hardware, firmware, and systems teams. The position offers a target base salary of $180,000–$260,000 per year plus equity, benefits, and a 401(k).
