Serdes IP Design Engineer at Synopsys

Synopsys is seeking a Digital Design Engineer to join a mixed-signal design and verification team focused on high-speed SERDES PHY IP, including USB4, PCIe, Ethernet, DisplayPort, HDMI, and MIPI products up to 40 Gbps. The role covers digital design methodologies, ATE production testing, DFT, synthesis constraints, functional and performance testing, and collaboration with analog, physical design, and customer-support teams. Candidates need an MSEE or BSEE, at least three years of digital design and verification experience, Verilog and VCS knowledge, and familiarity with back-end synthesis tools; scripting, data recovery, and RTL coding experience are preferred.