Silicon Design for Test Engineer at Google

Seniority in posting: Mid

Compensation

$163,000 – $236,000/yr

Location: Austin, Texas · Mountain View, California
Type: Full-time
Level: senior
Posted: Aug 19, 2026

Description

Google is hiring a Silicon Design for Test Engineer to partner with cross-functional teams on custom silicon solutions. The role involves architecting and verifying design-for-test solutions, developing custom DFT methodologies, creating and optimizing production test patterns, and mentoring peers. Candidates need a bachelor's degree in electrical engineering or a related field, equivalent practical experience, and 8 years of experience in high-performance IP or SoC design-for-test activities and flows. Preferred qualifications include advanced degrees, AI/ML-assisted DFT techniques, scripting, data mining, silicon bring-up, and validation experience. The position offers $163,000–$236,000 USD plus a 15% bonus target, equity, and benefits, with interviews typically conducted in person and work locations in Austin, Texas, or Mountain View, California.

Required Skills

DFT
ATPG
Logic Vision
BIST
JTAG
Python
Tcl
Perl
Data mining
Silicon bring-up

Additional Information

Minimum Education: Bachelor's degree in Electrical Engineering or a related field, or equivalent practical experience
Required Previous Experiences: 8 years of experience in high-performance IP or SoC design-for-test activities and flows
Experience developing, deploying, and supporting DFT flows using ATPG, Logic Vision, BIST, or JTAG
Preferred Qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field
Experience applying AI/ML-assisted DFT design techniques for scaling and physical design closure
Experience scripting in Python, Tcl, or Perl and data mining for quality-of-return metrics
Experience developing novel DFT solutions, silicon bring-up, and validation
Knowledge of high-performance, low-power design DFT techniques and end-to-end silicon flows