Description
Lattice is hiring a Silicon Design Validation engineer to validate and characterize FPGA building blocks and high-speed IPs from silicon arrival through product release. The role involves developing validation plans, test logic RTL, automation scripts, and performing bring-up, debug, data analysis, and cross-functional support for issues after release. The position requires 5+ years of experience, an Electrical Engineering degree, strong expertise in high-speed serdes and protocol compliance testing, FPGA tools, Verilog/VHDL, Python/Perl automation, and bench equipment; the base pay is $118,000 to $148,000 per year plus bonus and equity.
