Description
Google DeepMind is hiring an ASIC Power Analysis and Optimization Engineer to architect power solutions, automate RTL power analysis and optimization flows, integrate power-management IP, and support power reduction from SoC architecture through sign-off. The role requires seven years of ASIC power-analysis and optimization experience, including production-chip work, tape-outs, foundry collaboration, Verilog, EDA tools, scripting, and software development. Compensation is $217,000–$236,000 USD plus a 15% bonus target.
