Silicon Validation Manager at Synopsys

Language

Location: Oeiras
Level: lead/mgmt
Posted: Aug 28, 2026

Description

Synopsys is hiring a High-Speed Analog Silicon Validation Engineering Manager in Lisbon to lead silicon validation operations for high-speed analog IP. The role manages lab resources, SerDes testing and characterization, silicon debugging, validation reporting, custom test hardware, and a team of engineers, while collaborating with design, applications, and product management. Candidates need at least five years of analog or mixed-signal silicon validation experience, team-management experience, a relevant engineering degree, strong analog and SerDes knowledge, protocol familiarity, and programming skills in MATLAB, Python, or equivalent tools.

Required Skills

Silicon validation
SerDes validation
Signal integrity
Test automation
MATLAB
Python
FPGA testing
Verilog
VHDL

Additional Information

Minimum Education: Degree in Electronic Engineering, Electrical Engineering, or a related technical discipline
Required Previous Experiences: 5+ years of silicon validation, test, or characterization experience for analog or mixed-signal integrated circuits
Experience managing technical teams, including project planning, resource allocation, performance evaluation, and engineer development
Experience building team capability and delivering results while maintaining technical quality standards
Experience with FPGA-based test systems and familiarity with Verilog or VHDL for custom test logic
Preferred Qualifications: Experience with FPGA-based test systems and familiarity with Verilog or VHDL for custom test logic