SOC Clock Distribution Engineer at NVIDIA

NVIDIA is hiring a Physical Design Engineer for its System-On-Chip (SOC) group to design and implement SOC-level clock requirements, perform chip-level design activities including partitioning, CDC, trial synthesis, and design quality checks, and support functional debugging and physical design readiness. The role requires a B.S. in Electrical or Computer Engineering, at least three years of chip design experience, hands-on physical design and clock distribution skills, and proficiency in a scripting language such as Perl, Python, Bash, or Tcl.