Description
NVIDIA is hiring a Physical Design Engineer for its System-On-Chip (SOC) group to design and implement SOC-level clock requirements, perform chip-level design activities including partitioning, clock-domain crossing, trial synthesis, and design-quality checks, and resolve functional and physical design issues. The role involves complex networking-chip development and collaboration with Physical Design, CAD, Package Design, Software, DFT, and other teams. Candidates need an electrical or computer engineering degree, at least three years of chip-design experience, hands-on clock-distribution skills in tightly constrained products, and proficiency in a scripting language such as Perl, Python, Bash, or Tcl.
