SOC Clocks RTL Design Engineer at NVIDIA

Department: Engineer, ASIC

Language

Setup: On-site
Location: Tel Aviv, Tel-Aviv District · Ashkelon, South District · +1
Type: Full-time
Level: mid
Posted: Aug 1, 2026

Description

NVIDIA is hiring an RTL Design Engineer to own the clocking logic for next-generation networking System-On-Chip designs. The role covers clock generation, distribution, PLL and reference-clock integration, muxing, dividers, glitchless switching, gating, reset synchronization, clock-domain-crossing infrastructure, and clock-tree implementation through tape-out. The engineer will translate micro-architecture specifications into synthesizable Verilog or SystemVerilog, collaborate with micro-architecture, verification, physical design, CAD, software, and DFT teams, and support emulation, firmware, and post-silicon bring-up. The posting requires a B.Sc. or M.Sc. in Electrical or Computer Engineering, at least three years of relevant RTL/logic design experience, and strong knowledge of clocking, reset, synthesis, timing, and design-quality tooling.

Required Skills

Verilog/SystemVerilog
Clocking and reset
Clock domain crossing
Synthesis
Timing
PLL integration
Clock tree constraints

Additional Information

Minimum Education: B.Sc. or M.Sc. in Electrical Engineering or Computer Engineering
Required Previous Experiences: At least 3 years of relevant RTL/logic design experience
Experience taking a design from micro-architecture specification through verification and physical implementation
Prior ownership of SOC-level clocking or reset architecture on a taped-out chip
Preferred Qualifications: Passion for quality and a track record of clean deliveries to downstream customers
Experience with PLL/clock generator integration and clock tree constraint development with backend teams
Translation Company Name: NVIDIA