Description
Google is hiring a TPU SoC Design Engineer to define and implement high-performance, power-efficient digital designs for data-center AI accelerators. The role focuses on SoC-level RTL architecture, SystemVerilog coding, global communication buses, ASIC integration, microarchitecture documentation, verification collaboration, physical-design requirements, and design-flow development. Candidates need a relevant bachelor's degree or equivalent practical experience and at least two years of RTL architecture experience, along with experience using industry-standard EDA tools.
