Qualcomm International Inc., Mexico Branch Office

SoC Design Implementation Engineer (Up to Principal Level) at Qualcomm International Inc., Mexico Branch Office

Department: Hardware Engineering

Language

Setup: On-site
Location: Ho Chi Minh City
Level: not_specified
Posted: Sep 15, 2026

Description

Qualcomm Vietnam Company Limited is hiring an SoC Design Implementation Engineer to support the RTL-to-gate implementation of complex SoC, subsystem, and IP designs. The role covers synthesis, timing and QoR analysis, constraint development, UPF-based low-power implementation, netlist generation, design-quality debugging, and handoff to downstream physical design, DFT, verification, emulation, and signoff teams. It includes Engineer, Senior Engineer, Staff/Senior Staff Engineer, and Principal Engineer levels, with a bachelor’s degree and 3+ years of relevant front-end experience as the minimum qualification.

Required Skills

RTL design
Synthesis
Timing constraints
UPF
Verilog
SystemVerilog
Tcl
Python

Additional Information

Minimum Education: Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field
Required Previous Experiences: 3+ years of relevant experience in RTL design, SoC integration, synthesis, ASIC/FPGA development, or front-end implementation
Experience with at least one RTL development or front-end implementation flow from design through synthesis or implementation handoff
Preferred Qualifications: Experience with synthesis tools, static timing analysis tools, equivalence checking, lint, CDC/RDC, or related front-end quality tools
Practical experience with UPF, power domains, isolation, level shifters, retention, power states, or power-aware verification
Experience with multi-mode, multi-corner constraints and timing closure across block, subsystem, or SoC designs
Knowledge of ASIC implementation flows, DFT, physical design handoff, emulation, FPGA prototyping, or gate-level simulation
Proficiency in Tcl, Python, Perl, Shell, or similar scripting languages for flow automation and report analysis
Experience with AXI, AHB, APB, or other standard on-chip interfaces
Experience working in a large, globally distributed semiconductor engineering organization