Description
Qualcomm is hiring a Design Verification Engineer for its Data Center SoC Verification team. The role develops and executes verification plans, builds System Verilog/UVM and processor-based verification environments, creates random test scenarios, develops coverage models, debugs RTL and integration issues, and drives coverage closure for complex data-center SoCs including CPUs, cache coherency, memory, interconnects, AI/ML accelerators, and security features. Candidates need a bachelor's, master's, or PhD in a relevant field and at least one year of ASIC design, verification, validation, integration, or related experience, with a minimum of two years for senior positions. The listed pay range is $121,800 to $182,600.
