Description
The role is responsible for defining DFT specifications, creating verification plans and SoC test interfaces, developing and integrating DFT architecture into large SoC blocks, implementing testbenches and directed and constrained-random tests, debugging failures, running gate-level simulations, and achieving first-tapeout success. The position also supports STA, physical, power, and logical analysis for DFT modes and collaborates with Chip Architecture, DV, Physical Design, and Power teams. Candidates need a degree in Electrical Engineering, Computer Science, or a related field, DFT knowledge including ATPG, JTAG, and MBIST, Verilog or VHDL proficiency, scripting ability, and strong English communication skills.
