Description
The role leads SoC digital design-for-test (DFT) architecture and the complete DFT lifecycle from RTL planning through post-silicon production release qualification. Responsibilities include defining DFT architectures for multi-core SoCs, managing schedules and resources, deploying automation flows, collaborating with physical design and power architects, supporting PRQ, mentoring senior staff, and acting as the primary technical liaison for DFT matters. The position requires a bachelor's degree in electrical or computer engineering, 10 years of SoC DFT and DFT-protocol experience, 10 years of EDA-tool experience, 4 years of people-management experience, and experience with Tcl, Python, or Perl.
