Soc Engineer (Physical Design) at Synopsys

Synopsys is hiring a Senior SOC Engineer to develop and implement SOC designs from Verilog through GDS using Synopsys EDA tools and IP. The role involves turnkey projects, customer advisory, independent problem solving, schedule management, cross-functional collaboration, and mentoring junior team members. Candidates need a BS/MS/PhD in Electronics Engineering, Electromechanics, or Telecommunications, 5–10 years of Place & Route experience with Fusion Compiler/ICC2, knowledge of P&R, extraction, timing, IREM, and Physical Verification, and proficiency in TCL and PERL.