Description
Synopsys is hiring a Principal Engineer (STA) in Bengaluru to own block-level static timing analysis signoff and contribute to full-chip timing closure for advanced process nodes. The role includes STA debugging, constraint development and validation, power analysis, ECO support, tool correlation, automation, and collaboration with design, physical design, synthesis, and verification teams. Candidates need a bachelor’s or master’s degree in electronics, electrical engineering, or a related field, 10+ years of relevant STA and timing-closure experience, strong Synopsys tool proficiency, and scripting skills in TCL, Python, or Perl.
