SoC Engineering, Principal Engineer-18586 at Synopsys

Synopsys is hiring a Principal Engineer for SoC Engineering, focusing on leading complex ASIC digital subsystems from requirements and architecture through RTL implementation, verification, DFT, and silicon release. The role requires an advanced degree and at least 8 years of RTL design and subsystem architecture experience, expertise in Verilog/System Verilog, protocols such as UCIe, Ethernet, UALink, and AMBA, and strong leadership and mentoring capabilities. The position is based in Sunnyvale, California, is not eligible for remote work, and offers a base salary of $191,000 to $286,000 plus potential bonus, equity, and other benefits.