Description
Synopsys is hiring a Static Timing Analysis (STA) Engineer to own block-level STA signoff and contribute to full-chip timing closure for advanced process nodes. The role includes STA debugging, constraint development and validation, power analysis and ECO support, tool correlation, automation with TCL, Python, or Perl, and collaboration with design, physical design, synthesis, and verification teams. Candidates need a bachelor’s or master’s degree in electronics, electrical engineering, or a related field, extensive STA and timing closure experience, and proficiency with Synopsys tools such as PrimeTime.
