SOC Engineering, Sr Engineer - 18640 at Synopsys

Synopsys is hiring a Senior SOC Engineer to design, review, and debug RTL for block-level SoC subsystems, including state machines, pipelines, FIFOs, and memory controllers. The role covers RTL quality checks, verification debugging, timing closure, interface protocols, scripting, design reviews, and reusable IP development for automotive, aerospace, defense, and high-performance computing customers. Candidates need a bachelor's or master's degree in electrical or computer engineering and 3–4 years of ASIC or FPGA RTL design, implementation, and debug experience. The position is based in Sunnyvale, California, is not remote, and offers a base salary of $112,000–$169,000 plus potential bonus, equity, and other benefits.