SOC Engineering, Sr Staff Engineer at Synopsys

Synopsys is hiring a DDR/HBM Physical Design Engineer to implement DDR and HBM PHYs for customer ASICs and SOCs, taking designs from RTL through physical implementation, timing closure, signoff, synthesis, place-and-route, physical verification, design-for-test, and ATPG. The role requires leading design engagements, coordinating with internal and customer teams, debugging complex timing, power, and physical-design issues, and mentoring junior engineers on advanced-node physical design. Candidates need at least five years of ASIC physical-design experience, multiple successful tapeouts on advanced nodes, and experience with Synopsys tools and FinFet process technologies.