Description
Synopsys is hiring a Static Timing Analysis (STA) Engineer to own block-level STA signoff and contribute to full-chip timing closure for advanced process nodes. The role includes STA debugging, constraint development and validation, power analysis, ECO support, tool correlation, and automation using Synopsys tools and TCL, Python, or Perl. Candidates need a bachelor’s or master’s degree in electronics, electrical engineering, or a related field, at least 8 years of STA and timing closure experience, and strong proficiency with PrimeTime and related signoff methodologies.
