Description
Synopsys is hiring a Senior / Staff ASIC/SoC Design Verification Engineer in Ho Chi Minh City, Vietnam. The role executes the full RTL functional verification lifecycle for IP, subsystem, and SoC projects; develops UVM-based verification environments and reusable components; creates functional coverage and System Verilog Assertions; debugs complex issues with VCS and Verdi; and collaborates with global teams and customers. The position requires at least three years of ASIC/SoC design verification experience, proficiency in Verilog and System Verilog, UVM expertise, protocol knowledge, and scripting skills. It is not remote-eligible and offers health, wellness, and financial benefits.
