SOC Engineering, Staff Engineer - 18430 at Synopsys

Synopsys is hiring a SoC Verification Staff Engineer in District 7, Ho Chi Minh City, Vietnam, to define verification plans, build System Verilog and UVM testbenches, develop constrained-random and directed tests, debug RTL and testbench failures, collaborate with RTL designers, apply formal verification, and drive coverage to signoff. The role requires a bachelor's or master's degree in a relevant engineering or computer science field, at least six years of semiconductor design verification experience, strong System Verilog and UVM skills, knowledge of a semiconductor protocol, experience with industry simulators and version control, and scripting ability in Python, Perl, or Tcl.