SOC Engineering, Staff Engineer - 18846 at Synopsys

Synopsys is hiring a Senior Staff SoC RTL Design Engineer in Noida, India, to perform RTL quality signoff, timing constraints, synthesis validation, formal equivalence checking, IP integration, and customer-specific RTL design for complex semiconductor SoCs. The role requires a bachelor's or master's degree in a relevant engineering field and at least 8 years of hands-on RTL design and verification experience, with strong expertise in Spyglass, Design Compiler or Fusion Compiler, Formality, clock-domain crossing, and SoC integration. The position is not remote-eligible and is part of Synopsys's System Solutions Group.