SoC Management Subsystem Architect at Majestic

Department: Engineering

Setup: On-site
Location: Los Altos, California
Type: Full-time
Level: senior
Added to Metaintro: Sep 24, 2026

Description

Majestic Labs is hiring a SoC Architect to lead the design and integration of the management subsystem for its AI acceleration platform. The role owns architecture for control and management flows, integrates ARM cores and subsystems, designs PCIe and high-bandwidth I/O, DDR/LPDDR interfaces, peripheral buses, scheduler and interrupt schemes, and debug infrastructure, and collaborates with hardware, firmware, RTL, verification, and board teams. The position requires a bachelor’s or master’s degree in electrical or computer engineering and at least six years of SoC architecture and design experience.

Required Skills

ARM cores
PCIe connectivity
DDR/LPDDR interfaces
Peripheral interfaces
Interrupt management
CoreSight

Additional Information

Minimum Education: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field
Required Previous Experiences: 6+ years of SoC architecture and design experience, with emphasis on management or control subsystems
Experience integrating ARM cores, PCIe, DDR/LPDDR, and peripheral interfaces
Hands-on experience in control path design, driver interfaces, and interrupt management
Preferred Qualifications: Experience with AI/ML acceleration hardware or high-performance compute SoCs
Knowledge of board-level integration and hardware-software co-validation
Familiarity with silicon prototyping, emulation, or FPGA-based validation
Expertise in low-power design and high-bandwidth interconnect architectures
Deep experience with CoreSight, trace analyzers, profilers, and performance instrumentation
Translation Company Name: Majestic Labs