SoC Physical Design Engineer at Nokia

The role focuses on physical design implementation of Optical Network ASICs, including floor planning, place-and-route, power and clock distribution, physical verification, timing closure, static timing analysis, IR/EM analysis, and GDSII generation. The engineer will collaborate with logic and hardware teams, evaluate IP vendors and process nodes, develop physical-design methodologies and automation scripts, and support design trade-offs. The posting requires at least three years of ASIC physical-design experience in 3/5 and 7nm nodes, full-cycle IC-design knowledge, EDA tool experience, scripting ability, and a bachelor's degree or higher in a relevant electrical or VLSI field.