SoC Physical Design Engineer, PnR at Apple

The role is responsible for the physical implementation of design partitions from netlist through GDS2 tapeout for a highly complex system-on-chip. Responsibilities include collaborating with the logic design team, completing netlist-to-GDS2 implementation, performing timing, physical, and electrical verification, driving signoff closure, and resolving physical-design and flow issues. The minimum qualifications are a bachelor's degree and at least three years of relevant industry experience; preferred qualifications include partition-level physical design and verification, large SOC experience, sub-10nm technology, and industry-standard tool knowledge.