Description
Apple is hiring a Physical Design Engineer to implement design partitions from netlist through GDS2 tapeout for a highly complex SOC. The role collaborates with architecture, CAD, timing, and logic design teams and covers physical synthesis, floorplanning, place-and-route, power grid, timing signoff, DRC/LVS, and EMIR verification. The minimum qualification is a bachelor's degree and basic logic-gate knowledge; relevant coursework, teamwork, and experience with Verilog, VHDL, Python, Perl, TCL, or SPICE are preferred.
